1. Field of the Invention
The present invention relates to Peripheral Component Interconnect (PCI) and PCI-X interfaces and, more particularly, to a device having a PCIXCAP pin input and circuitry that selectively enables use of the pin input for detecting PCI/PCI-X bus mode or for generating a DC output signal.
2. Background Art
Peripheral Component Interconnect (PCI) interfaces have been used to provide high-speed connectivity between devices in a multi-device system, such as a processor based system such as a personal computer.
FIG. 1 is a diagram illustrating a conventional implementation of a PCI bus system architecture 100. The system 100 includes a processor 102 coupled to a memory controller 104 via a local bus 106′. The processor 102 and the memory controller 104 are coupled to a PCI local bus 106 (labeled PCI Local Bus #0) via a host bridge 108.
The host bridge 108 provides a low latency path through which the processor 102 may directly access PCI devices 110, for example a network interface card 110a providing access to a local area network 112, a disc drive (SCSI) controller 110b providing access to disk drives 114, an audio card 110c, a motion picture card 110d, or a graphics card 110e configured for driving a monitor 116. The host bridge 108 also provides a high bandwidth path allowing PCI masters on the PCI bus 106 direct access to the system memory 118 via the memory controller 104. A cache memory 120 is independent of the system memory 118 for use by the processor 102.
The term “host bridge” refers to the bridge device 108 that provides access to the system memory 118 for the devices 110 connected to the PCI bus 106. A PCI-to-PCI bridge 122 also may be used to connect a second PCI bus 124 to the PCI bus 106, the second PCI bus 124 configured for connecting other I/O devices 126.
Newer PCI bus protocols are being published, including PCI-X Mode 1 and Mode 2, that provide enhanced PCI functionality. These newer PCI bus protocols include the PCI Local Bus Specification, Rev 2.3, the PCI-X Protocol Electrical and Mechanical Addendum to the PCI Local Bus Specification, Rev. 2.0a, and the PCI-to-PCI Bridge Architecture Specification, Rev 1.2.
The newer PCI host bridge devices may utilize HyperTransport™ technology, which specifies a data rate of 1.6 GHz between each differential signal pair. Hence, the newer PCI bus devices need to be implemented using newer semiconductor fabrication process technology to optimize the higher speed requirements of HyperTransport™ technology.
The PCI-X Specification defines a PCIXCAP pin for detecting a PCI/PCI-X Bus mode. The circuitry associated with the PCIXCAP pin includes voltage level detection logics that determine the type of add-in card that is present. Once the PCI/PCI-X mode is detected, the bus is set to the proper mode. Thus, for example, add-in cards indicate that they are capable of PCI-X operation by connection of the PCIXCAP pin on the add-in card connector.
In addition, a PCI Hot-plug specification has been defined so that electronic components can be installed and/or removed from a PCI bus devices while the computer is running. Typically without the Hot-plug mode, when a card fails, the system (e.g., computer) must be powered off to attend to the failed device. Using the Hot-plug mode, when a card fails, the failure is reported by the system and the individual slot on a PCI bus is selectively powered off to permit the card to be removed from and/or installed into the slot without the need to power off the entire system.
Since support must be provided for different PCI/PCI-X bus modes, a large number of pin inputs are required on an integrated (e.g., single chip) device that detects the bus mode. Thus, there is a need to utilize the PCIXCAP pin input as a DC pin input when the PCIXCAP pin input is not used to detect the mode of PCI-PCI-X operation.